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rev. 1.51 january 2008 fbdimm ddr2 sdram 1 of 33 ddr2 fully buffered dimm 240pin fbdimms based on 512mb e-die (rohs compliant) 60fbga with lead-free * samsung electronics reserves the right to change products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or other- wise, to any intellectual property rights in samsung products or technol- ogy. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sa msung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, me dical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmen tal procurement to which special terms or provisions may apply.
rev. 1.51 january 2008 fbdimm ddr2 sdram 2 of 33 1. features ................. ................ ................. ................ ................ ................. ................ ............ ........4 2.0 fbdimm generals ........ ................. ................ ................ ................. ................ ................. ..........5 2.1 fb-dimm operation overview ................ ................ ................. ................ .............. .............. .............5 2.2 fb-dimm channel frequency scaling .............. ................. ................ ................. ................ ......... ......6 2.3 fb-dimm clocking scheme ................. ................ ................ ................. ................ .............. .............7 2.4 fb-dimm protocol ................ ................ ................ ................. ................ .............. .............. .............7 2.5 southbound command delivery ................. ................ .............. .............. .............. .............. .............8 2.6 basic timing diagram ............... ................. ................ .............. .............. .............. .............. .............9 2.7 advanced memory buffer block diagram ................ ................. ................ .............. .............. ...........11 2.8 interfaces ................. ................ ................. ................ ................ ................. .............. .............. ..... 12 3.0 fbd high-speed differential point to point link (at 1.5 v) interf ace ...............12 3.1 ddr2 channel ................ ................ ................. ................ ................ ................. .............. .............1 2 3.2 smbus slave interface ................. ................ .............. .............. .............. .............. .............. ...........12 3.3 fbd channel latency ............... ................. ................ .............. .............. .............. .............. ...........13 3.4 peak theoretical throughput ................... ................. ................ .............. .............. .............. ...........13 3.5 hot-add ................. ................ ................ ................. ................ ................. .............. .............. ........13 3.6 hot remove ................ ................. ................ ................ ................. ................ .............. .............. ....13 3.7 hot replace ................ ................. ................ ................ ................. ................ .............. .............. ....13 4.0 pin configureation ...... ................ ................ ................. ................ ................. ................ ......14 5.0 fbdimm functional block diagram ................. ................ ................. ................ .............16 5.1 512mb, 64mx72 module - m395t6553ez4 ................ ................. ................ .............. .............. ...........16 5.2 1gb, 128mx72 module - m395t2953ez4 .............. ................ ................ ................. ................ ...........17 5.3 2gb, 256mx72 module - m395t5750ez4 .............. ................ ................ ................. ................ ...........18 6.0 electrical characteristics ...... ................. ................ .............. .............. .............. ...........19 7.0 channel initialization .. ................ ................. ................ ................. ................ ................ ....27 table of contents
rev. 1.51 january 2008 fbdimm ddr2 sdram 3 of 33 revision history revision month year history 1.0 november 2006 - first released. 1.1 january 2007 - added amb revision 1.2 february 2007 - added idt a1.5 fbd, corrected dimm thickness(8.0mm to 8.2mm) 1.3 april 2007 - changed amb device operation temperature symbol(tj to tcase) 1.4 june 2007 - added 800 fbd 1.5 october 2007 - added nec d1 fbd, removed nec b5+ fbd 1.51 january 2008 - typo correction
rev. 1.51 january 2008 fbdimm ddr2 sdram 4 of 33 1. features - 240pin fully buffered dual in-line memory module (fb- dimm) - 3.2gb/s, 4.0gb/s, 4.8gb/s link transfer rate - 1.8v +/- 0.1v power supply for dram v dd /v ddq - 1.5v +0.075/-0.045v power supply for amb v cc - 3.3v +/- 0.3v power supply for v ddspd - buffer interface with high-speed differential point-to- point link at 1.5 volt - channel error detection & reporting - channel fail over mode support - serial presence detect with eeprom - 4 banks - posted cas - programmable cas latency: 3, 4, 5, 6 - automatic ddr2 dram bus and channel calibration - mbist and ibist test functions - hot add-on and hot remove capability - transparent mode for dram test support table 1 : ordering information note : 1. ?z? of part number(11th digit) stands for lead-free products. 2. the last digit stands for amb. part number density organization component composition number of rank amb type of heat spreader height m395t6553ez4-cd55/e65 512mb 64m x 72 64mx8(k4t51083qe) * 9ea 1 intel d1 full module 30.35mm m395t6553ez4-cd56/e66/f76/e76 idt c1 m395t6553ez4-cd51/e61 idt a1.5 m395t6553ez4-cd57/e67 nec d1 m395t2953ez4-cd55/e65 1gb 128m x 72 64mx8(k4t51083qe) * 18ea 2 intel d1 m395t2953ez4-cd56/e66/f76/e76 idt c1 m395t2953ez4-cd51/e61 idt a1.5 m395t2953ez4-cd57/e67 nec d1 m395t5750ez4-cd55/e65 2gb 256m x 72 128mx4(k4t51043qe) * 36ea 2 intel d1 m395t5750ez4-cd56/e66/f76/e76 idt c1 m395t5750ez4-cd51/e61 idt a1.5 m395t5750ez4-cd57/e67 nec d1 table 2 : performance range e7(ddr2-800) f7(ddr2-800) e6(ddr2-667) d5(ddr2-533) unit ddr2 dram speed 800 800 667 533 mbps cl-trcd-trp 5-5-5 6-6-6 5-5-5 4-4-4 ck table 3 : address configuration organization row address column address bank address auto precharge 64mx8(512mb) based module a0-a13 a0-a9 ba0-ba1 a10 128mx4(512mb) based module a0-a13 a0-a9, a11 ba0-ba1 a10
rev. 1.51 january 2008 fbdimm ddr2 sdram 5 of 33 2.1 fb-dimm operation overview fb-dimm (fully buffered dual in line memory module) is designe d for the applications which require higher data transfer bandwid th and scalable memory capacity. the memory slot access rate per channel decreases as the memory bus speed increases, resulting in lim ited density build-up as channel speeds increase with memory system hav ing the stub-bus architecture. fb-dimm solution is intended t o eliminate this stub-bus channel bottleneck by using point-to-point links that enable multiple memory modules to be connected se rially to a given channel. memory system architecture persp ective, fb-dimm is fully differ entiated from registered dimm a nd unbuffered dimm. a lot of new technologies are integrated into this solution in order to achi eve this scalable higher speed memory solution. serial link inte rface with packet data format and dedicated read/write paths are key attrib ute in fb-dimm protocol. point to point interconnect with fully differential signaling and de-emphasis scheme are key attrib ute in fbd channel link. clock recovery by using data stream is key attribute in fbd clocking. fb-dimm supports both clock resync and resampling mode options. crc (cyclic redundancy check) bits are transferred wi th data stream for reliability at high speed data transaction. failov er mechanism supports system running with dynamic io failure. finally all fb-dimm is connected in daisy chain manner. thus, every interc onnection between amb (advanced memory buffer) to amb, amb to host and amb to dram, is point to point interconne ction which allows higher data transfer bandwidth. figure 1 shows a lot of new technologies integrated with fbd solution. figure 1 : fb-dimm memory system overview host dram dram amb dqs addr cmd clk tx tx rx rx clk_ref p2p interconnect - lvds - de-emphasis reliability - crc fail-over clock recovery two unidirectional links - northbound - southbound protocol packet addr.cmd, data sb (addr, cmd, wdata) nb(rdata) dram dram amb tx tx rx rx clock dqs addr cmd clk fifo buffer daisy chain connection upto 8 amb dimm topology fly-by clk, cmd 2.0 fbdimm generals
rev. 1.51 january 2008 fbdimm ddr2 sdram 6 of 33 figure 2 : fb-dimm speed scaling host dram dram amb dqs addr cmd clk tx tx rx rx clk_ref sb (addr, cmd, wdata) nb(rdata) dram dram clock reference clk reference clk ddr667 ex. 6ns 3ns 250ps clk_ref clk_dram packet t/f 12 uis in one clk_dram ui clk_dram clk_ref frequency ddr2-533 312.5ps 266mhz 133mhz 3.2gb/s ddr2-667 250ps 333mhz 166mhz 4.0gb/s ddr2-800 208.33ps 400mhz 200mhz 4.8gb/s 2.2 fb-dimm channel frequency scaling there are many frequency parameters including reference clock fr equency, dram clock frequency, dram data transfer rate, channel transfer rate and channel unit interval. all of frequency paramete rs are scaled with a certain gear ratio. external clock sourc e provides reference clock input to amb and host. external clock source is relatively slower than channel and dram frequency. thus, amb do u- bles external clock input and generates clock inputs to drams. dra m use clock input from amb which is two times faster than ref er- ence clock for dram operation. dram data transfer rate is two ti mes faster than dram clock input with nature of double data rat e operation and four times faster than external clock source. channel speed is represented by unit interval - average time interv al between voltage transitions of a signal in the fbd channel. it is six ti mes faster than dram data transfer rate. for example, external clock source gives 6ns clock (166mhz), amb doubles it and gives 3ns clock (3 33mhz) to dram and fbd channel communicate with unit interval - 250ps (4.0gbps transfer rate). figure 2 shows frequency scale ratio over frequency parameters in fbd memory system.
rev. 1.51 january 2008 fbdimm ddr2 sdram 7 of 33 2.4 fb-dimm protocol fb-dimm channel has two unidirectional communication paths - south bound and north bound. south bound and north bound use phys- ically different signal path. south and north mean direction of signal transaction. southbound means direction of signals runni ng from the host controller toward the dimms. north is the opposite of south. due to nature of memory operation, southbound carries informa tion including command to dram, address to dram and write data to dra m, while north bound carries read data from dram. in channel protocol point of view, southbound and northbound have different data frame formats and frame format size is optimized to ratio of read and write. data transfer perspective, read data transfer rate of north bound is twice faster than write data transfer. higher c hannel utiliza- tion achieves with asymmetric read and write data transfer rate. figure 3 : fb-dimm clocking figure 4 : southbound / northbound frame format southbound consists of 10 differential si gnal pairs (lane), physically 20 signaling line. southbound format has 10x12 (10 io (o r lane) x 12 io switching) frame format, which deliver 10x12 bit informa tion per one dram clock. one south bound frame is divided into th ree command slot. see figure 5. command slot a delivers command (with address). command slot b and c delivers command (with address) or write data into dram. host dram dram amb dqs addr cmd clk tx tx rx rx clk_ref sb (addr, cmd, wdata) nb(rdata) dram dram clock reference clk using reference clk (not in phase) clock recovery adjust edge/phase by; min. transition density min. transition density 6 transitions command (with address) command (with address) or write data in command (with address) or write data in r_data(x72bits) r_data(x72bits) a cmd b cmd c cmd sout bound northbound 512 transfers 2.3 fb-dimm clocking scheme in fb-dimm platform design, phase adjustm ent among reference clock inputs to each i ndividual amb and host is not taken account. thus, clock synchronization is made by us ing both external reference cl ock and channel data stream in fb-dimm memory system. ho st and each individual amb has a each individual io basis clock reco very circuitry for channel data communication. it runs with in puts from pll inside chip and data stream from the ot her amb or host. because data stream itself involves data communication process, no sig- naling switching or data communication may loss clock synchroni zation between transmitter and receiver. thus, min transition de nsity is defined for this purpose. in fbd channel, a density of 6 transiti ons within 512 transfers or unit intervals (ui) on the channel is required for interpolator training.
rev. 1.51 january 2008 fbdimm ddr2 sdram 8 of 33 figure 6 : fbdimm co mmand delivery rules note : 1. ae[0~12] : crc checksum of the a command 2. f[0~1] : frame type 3. fe[0~21] : crc checksum of 72bit data 4. crc : cyclic redundancy check 9876543210 0 ae0 ae7 ae8 f0=0 ac20 ac16 ac12 ac8 ac4 ac0 1 ae1 ae6 ae9 f1=0 ac21 ac17 ac13 ac9 ac5 ac1 2 ae2 ae5 ae10 ae13 ac22 ac18 ac14 ac10 ac6 ac2 3 ae3 ae4 ae11 ae12 ac23 ac19 ac15 ac11 ac7 ac3 4 fe21 0 0 0 bc20 bc16 bc12 bc8 bc4 bc0 5 fe20 0 0 0 bc21 bc17 bc13 bc9 bc5 bc1 6 fe19 0 0 0 bc22 bc18 bc14 bc10 bc6 bc2 7 fe18 0 0 0 bc23 bc19 bc15 bc11 bc7 bc3 8 fe17 0 0 0 cc20 cc16 cc12 cc8 cc4 cc0 9 fe16 0 0 0 cc21 cc17 cc13 cc9 cc5 cc1 10 fe15 0 0 0 cc22 cc18 cc14 cc10 cc6 cc2 11 fe14 0 0 0 cc23 cc19 cc15 cc11 cc7 cc3 fe0 fe7 fe11 fe1 fe6 fe10 fe2 fe5 fe9 fe13 fe3 fe4 fe8 fe12 note : the values in ? x? fields in non-reserved co mmands above may be driven onto the dram device pins. dram cmnds 2322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 activate ds2 ds1 ds0 1 dram addr rs dram bank & address write ds2 ds1 ds0 0 1 1 rs dram bank & address read ds2 ds1 ds0 0 1 0 rs dram bank & address precharge all ds2 ds1 ds0 0 0 1 rsxxxx1 1 1xxxxxxxxxx precharge single ds2 ds1 ds0 0 0 1 rs dram bank 1 1 0xxxxxxxxxx auto (cbr) refresh ds2 ds1 ds0 0 0 1 rsxxxx1 0 1xxxxxxxxxx enter self refresh ds2 ds1 ds0 0 0 1 rsxxxx1 0 0xxxxxxxxxx exit self refresh/ exit power down ds2 ds1 ds0 0 0 1 rsxxxx0 1 1xxxxxxxxxx enter power down ds2 ds1 ds0 0 0 1 rsxxxx0 1 0xxxxxxxxxx reserved xxx0 0 1xxxxx0 0xxxxxxxxxxx clk_ref clk_dram packet t/f 12 transfers x10 bits a cmd b cmd c cmd southbound command frame format* bit transfer figure 5 : fbdimm command encoding & sb frame ?a? ?b? ?c? ?c? ?a? ?b? 12345 fbd southbound cmd/data dimm 1 cmd dimm 2 cmd dimm 3 cmd dimm 4 cmd fbd northbound cmd/data 1. cmd a transferred immediately 2. cmd a, b, c cannot target the same dimm 3. host is responsible for scheduling cmd 2.5 southbound command delivery a dram command located in the "a" command may be delivered to the dram devices as soon as the 14-bit (10-bits in fail-over) crc is checked. this minimizes dram access la tency by allowing the command to be deliver ed after the first 4 transfers of the frame have been received. the "a" command is transferred immediately to t he dram pins with minimum delay whereas the "b" and "c" command are delivered one dram clock later. to minimize memory access la tency the read related activate, read (if the page is open) and explicit precharge commands to a rank of dram devices should be pl aced in the "a" command, if possible. figure 6 illustrates th e deliv- ery of the three potential commands in a fr ame to three separate dram channels. command "a" is delivered in this case to the dram devices on dimm 3 as soon as the command can traverse the amb buffer. the "b" and "c" commands are delayed and presented to two other dram channels on the following clock. see below figure7~10 for basic read & write operations northbound consists of 14 differential signal pairs (lane), physi cally 28 signaling line. southbound format has 14x12 (14 io (o r lane) x 12 io switching) frame format, which deliv er 14x12 bit information per one dram clock. one north bound frame is divided into tw o. both frame deliver read data from dram
rev. 1.51 january 2008 fbdimm ddr2 sdram 9 of 33 figure 7 : basic dram read data transfers on fbd figure 8 : back to back dram read data transfers act1 nop nop act1 12345 fbd southbound cmd/data dimm 1 cmd dimm 1 data dimm 2 cmd dimm 2 data fbd northbound data 6 7 8 9 10 11 12 13 rd1 nop nop rd1 act1 nop nop act1 12345 fbd southbound cmd/data dimm 1 cmd dimm 1 data dimm 2 cmd dimm 2 data fbd northbound data 12345678910111213 rd1 nop nop rd1 act2 nop nop rd2 nop nop act2 rd2 no bubble 2.6 basic timing diagram
rev. 1.51 january 2008 fbdimm ddr2 sdram 10 of 33 figure 9 : basic dram write data transfers on fbd figure 10 : simultaneous rd / wr data transfer s act1 nop nop act1 12345 fbd southbound cmd/data dimm 1 cmd dimm 1 data dimm 2 cmd dimm 2 data fbd northbound data 12345678910111213 wr1 wdata wdata wr1 nop wdata wdata nop wdata wdata nop wdata wdata sync 1010 0101 status act1 12345 fbd southbound cmd/data dimm 1 cmd dimm 1 data dimm 2 cmd dimm 2 data fbd northbound data 12345678910111213 rd1 wdata wdata rd1 act3 wdata wdata wr2 nop nop rd3 nop nop sync 1010 0101 status act2 wdata wdata act1 wdata wdata act3 rd3 act2 wr2 fixed fall through time
rev. 1.51 january 2008 fbdimm ddr2 sdram 11 of 33 figure 11 : advanced memory buffer block diagram advance memory buffer block dlagram demux data merge re-synch piso re-time 10x2 southbound data in 10x2 southbound data out 4 north pll 1x2 ref clock reset control reset# 10*2 10*2 link init sm and control and csrs mux lnit patterns ibist - tx ibist - rx failover command decoder & crc check thermal sensor lai logic mux mux ddr state controller and csrs 36 deep write data fifo external membist ddr calibration & ddr iobist/dfx core control and csrs data crc gen & read fifo cmd out data out data in sync & ldie pattern generator nb lai buffer mux ibist -tx ibist - rx demux data merge re-synch piso re-time 14x2 data out northbound 14*12 14*6*2 failover link lnit sm and control and csrs 14x2 data in northbound smbus controller smbus lai controller ddr ios dram clock 4 dram clock # 29 dram address / command copy 1 29 dram address / command copy 2 72 + 18x2 dram data / strobe dram cmd 2.7 advanced memory buffer block diagram
rev. 1.51 january 2008 fbdimm ddr2 sdram 12 of 33 2.8 interfaces figure12 illustrates the advanced memory buffer and all of it s interfaces. they consist of two fbd links, one ddr2 channel and an sm- bus interface. each fbd link connects the advanced memory buffer to a host memory controller or an adjacent fbd. the ddr2 chann el supports direct connection to the ddr 2 sdrams on a fully buffered dimm the fbdimm channel uses a daisy-chain topology to provide expan sion from a single dimm per channel to up to 8 dimms per channel . the host sends data on the southbound link to the first dimm where it is received and re driven to the second dimm. on the south bound data path each dimm receives the data and again redrives the dat a to the next dimm until the last dimm receives the data. the l ast dimm in the chain initiates the transmission of data in the direction of the host (a.k.a. northbound). on the northbound data path e ach dimm receives the data and re-drives the data to the next dimm until the host is reached. 3.0 fbd high-speed differe ntial point to po int link (at 1.5 v) interface the advanced memory buffer supports one fbd channel consisting of two bidirectional link interf aces using high-speed differenti al point- to-point electrical signaling. the southbound input link is 10 lanes wide and carries commands and write data from the host me mory controller or the adjacent dimm in the host direction. the southbound output link forwards this same data to the next fbd. the northbound input link is 14 lanes wide and carries read return data or status information fr om the next fbdimm in the chain back towards the host. the northbound output link forwards this information back towards the host and multiplexes in any read return data or status information that is generated internally. 3.1 ddr2 channel the ddr2 channel on the advanced memory buffer supports dire ct connection to ddr2 sdrams. the ddr2 channel supports two ranks of eight banks with 16 row/column r equest, 64 data signals, and eight check-bit signals. there are two copies of address and com- mand signals to support dimm routing and elec trical requirements. four-transfer bursts are driven on the data and check-bit lin es at 800 mhz. propagation delays between read data/check-bit strobe lanes on a given channel can differ. each strobe can be calibrated by har dware state machines using write/read trial and error (or equivalent implementation). hardware aligns the read data and check-bits to a single core clock. the advanced memory buffer provides four copies of the comm and clock phase references (clk[3:0]) and write data/check-bit. 3.2 smbus slave interface the advanced memory buffer supports an smbus interface to allow system access to configuration registers independent of the fbd link. the advanced memory buffer will never be a master on the sm bus, only a slave. serial smbus data transfer is supported at 100 khz. smbus access to the advanced memory buffer may be a requirement to boot a system. this provid es a mechanism to set link strength, frequency and other parameters needed to insure robust operation given platform specific configurations. it is also r equired for diagnostic support when the link is down. the smbus address straps located on the dimm connector are used by the advanced memor y buffer to get its unique id. amb nb fbd in link sb fbd out link secondary or to optional next fbd ddr2 channel primary or host direction nb fbd out link sb fbd in link memory interface smb figure 12 : advanced memory buffer interface block diagram
rev. 1.51 january 2008 fbdimm ddr2 sdram 13 of 33 3.3 fbd channel latency fbd channel latency is measured from the time a read request is driven on the fbd channel pins to the time when the first 16 by tes (2nd chunk) of read completion data is sampled by the memory controller. when not using the variable read latency capability, the latency for a specific fbdimm on an fbd channel is always equal to the latency for any other fbdimm on that channel. however, the latency for ea ch fbdimm in a specific configur ation with some number of fbdi mms installed may not be equal to the latency for each fbdimm in a configuration with some different number of fbdimms installed. as more dimms are added to the fbd channel, additional latency is re quired to read from each dimm on the channel. because the f bd channel is based on the point-to-point inte rconnection of buffer components between dimms, memory requ ests are required to trav el through n-1 buffers before reaching the nth buffer. the result is that a four dimm channel conf iguration will have greater idle read latency compared to a one dimm channel configuration. the variable read latency capability can be used to reduce latency for dimms closer to the host. the idle latencies listed in this section are representative of what might be achiev ed in typical amb designs. actual implement ations with latencies less than the values listed will have higher application performance and vice versa. 3.4 peak theoretical throughput an fbd channel transfers read completion data on the fbd northbound data connection. 144 bits of data are transferred for every fbd northbound data frame. this matches the 18-byt e data transfer of an ecc ddr dram in a single dram command clock. a dram burst of 8 from a single channel or a dram burst of four from two lock-stepped channels provid es a total of 72 bytes of data (64 byte s plus 8 bytes ecc). the fbd frame rate matches the dram command clock because of t he fixed 6:1 ratio of the fbd channel clock to the dram command clock. therefore, the northbound data connection will exhibit t he same peak theoretical throughput as a single dram channel. fo r ex- ample, when using ddr2 533 drams, the peak theoretical bandw idth of the northbound data connection is 4.267 gb/sec. write data is transferred on the fbd sout hbound command and data connection, via command+ wdata frames. 72 bits of data are tran s- ferred for every fbd command+wdata frame. two command+wdata frames match the 18- byte data transfer of an ecc ddr dram in a single dram command clock. a dram burst of 8 transfers from a single channel, or a burst of 4 from two lock-step channels pro vides a total of 72 bytes of data (64 bytes plus 8 bytes ecc). when the fbd frame rate matches the dram command clock, th e southbound command and data connection will exhibit one half the peak theoretical throughput of a single dra m channel. for example, when using ddr2 533 drams, the peak theoretical bandwidth of the southbound command and data connection is 2.133 gb/sec. the total peak theoretical throughput for a single fbd channel is defined as the sum of the peak theoretical throughput of the northbound data connection and the southbound command a nd data connection. when the fbd frame rate matches the dram command clock, this is equal to 1.5 times the peak theoretical throughput of a sing le dram channel. for example, when using ddr2 533 drams, the pea k theoretical throughput of a ddr2 533 channel would be 4.267 gb/sec, while the peak th eoretical throughput of an fbd-533 channel would be 6.4 gb/sec 3.5 hot-add the fbdimm channel does not provide a mech anism to automatically detect and report th e addition of a new fbdimm south of the cu r- rently active last fbdimm. it is assumed the system will be noti fied through some means of the addition of one or more new fbdi mms so that specific commands can be sent to the host controller to initialize the newly added fbdimm(s) and perform a hot-add rese t to bring them into the channel timing domain. it shou ld be noted that the power to the fbdimm socket must be removed before a hot-add fb dimm is inserted or removed. applying or removing the power to a fbdimm socket is a system platform function. 3.6 hot remove in order to accomplish removal of fbdimms, the host must perform a fast reset sequence targeted at the last fbdimm that will be retained on the channel. the fast reset re-establishes the appropriate last fbdimm so that the southbound transmission outputs of the la st active fbdimm and the southbound and northbound outp uts of the fbdimms beyond t he last active fbdimm are disabled. once the appropriat e outputs are disabled, the system can coordinate the procedure to remove power in preparation for physical removal of the fbdimm if needed. note that the power to the fbdimm socket must be removed before a hot-add fbdimm is insert ed or removed. applying or re - moving the power to a fbdimm socket is a system platform function. 3.7 hot replace hot replace of fbdimm is accomplished through combining the hot-remove and hotadd processes.
rev. 1.51 january 2008 fbdimm ddr2 sdram 14 of 33 table 4 : ddr2 240 pin fbdimm confi gurations (front side/back side) rfu = reserved future use. * these pin positions are reserved for forwarded clocks to be used in futu re module implementations ** these pin positions are reserved fo r future architecture flexibility 1. the following signals are crc bits and thus appear out of the normal sequence : pn12/pn12 , sn12/sn12 , pn13/pn13 , sn13/sn12 , ps9/ps9 , ss9/ss9. pin front pin back pin front pin back pin front pin back pin front pin back 1 v dd 121 v dd 31 pn3 151 sn3 61 pn9 181 sn9 91 ps9 211 ss9 2 v dd 122 v dd 32 pn3 152 sn3 62 v ss 182 v ss 92 v ss 212 v ss 3 v dd 123 v dd 33 v ss 153 v ss 63 pn10 183 sn10 93 ps5 213 ss5 4 v ss 124 v ss 34 pn4 154 sn4 64 pn10 184 sn10 94 ps5 214 ss5 5 v dd 125 v dd 35 pn4 155 sn4 65 v ss 185 v ss 95 v ss 215 v ss 6 v dd 126 v dd 36 v ss 156 v ss 66 pn11 186 sn11 96 ps6 216 ss6 7 v dd 127 v dd 37 pn5 157 sn5 67 pn11 187 sn11 97 ps6 217 ss6 8 v ss 128 v ss 38 pn5 158 sn5 68 v ss 188 v ss 98 v ss 218 v ss 9 v cc 129 v cc 39 v ss 159 v ss key 99 ps7 219 ss7 10 v cc 130 v cc 40 pn13 160 sn13 69 v ss 189 v ss 100 ps7 220 ss7 11 v ss 131 v ss 41 pn13 161 sn13 70 ps0 190 ss0 101 v ss 221 v ss 12 v cc 132 v cc 42 v ss 162 v ss 71 ps0 191 ss0 102 ps8 222 ss8 13 v cc 133 v cc 43 v ss 163 v ss 72 v ss 192 v ss 103 ps8 223 ss8 14 v ss 134 v ss 44 rfu* 164 rfu* 73 ps1 193 ss1 104 v ss 224 v ss 15 v tt 135 v tt 45 rfu* 165 rfu* 74 ps1 194 ss1 105 rfu** 225 rfu** 16 vid1 136 vid0 46 v ss 166 v ss 75 v ss 195 v ss 106 rfu** 226 rfu** 17 reset 137 dnu/m_test 47 v ss 167 v ss 76 ps2 196 ss2 107 v ss 227 v ss 18 v ss 138 v ss 48 pn12 168 sn12 77 ps2 197 ss2 108 v dd 228 sck 19 rfu** 139 rfu** 49 pn12 169 sn12 78 v ss 198 v ss 109 v dd 229 sck 20 rfu** 140 rfu** 50 v ss 170 v ss 79 ps3 199 ss3 110 v ss 230 v ss 21 v ss 141 v ss 51 pn6 171 sn6 80 ps3 200 ss3 111 v dd 231 v dd 22 pn0 142 sn0 52 pn6 172 sn6 81 v ss 201 v ss 112 v dd 232 v dd 23 pn0 143 sn0 53 v ss 173 v ss 82 ps4 202 ss4 113 v dd 233 v dd 24 v ss 144 v ss 54 pn7 174 sn7 83 ps4 203 ss4 114 v ss 234 v ss 25 pn1 145 sn1 55 pn7 175 sn7 84 v ss 204 v ss 115 v dd 235 v dd 26 pn1 146 sn1 56 v ss 176 v ss 85 v ss 205 v ss 116 v dd 236 v dd 27 v ss 147 v ss 57 pn8 177 sn8 86 rfu* 206 rfu* 117 v tt 237 v tt 28 pn2 148 sn2 58 pn8 178 sn8 87 rfu* 207 rfu* 118 sa2 238 v ddspd 29 pn2 149 sn2 59 v ss 179 v ss 88 v ss 208 v ss 119 sda 239 sa0 30 v ss 150 v ss 60 pn9 180 sn9 89 v ss 209 v ss 120 scl 240 sa1 90 ps9 210 ss9 4.0 pin configureation
rev. 1.51 january 2008 fbdimm ddr2 sdram 15 of 33 table 5 : pin description pin name type pin description pin numbers sck input system clock input, positive line 228 sck input system clock input, negative line 229 pn[13:0] output primary northbound data, positive lines 22, 25, 28, 31, 34, 37, 40, 48, 51, 54, 57, 60, 63, 66 pn [13:0] output primary northbound data, negative lines 23, 26, 29, 32, 35, 38, 41, 49, 52, 55, 58, 61, 64, 67 ps[9:0] input primary southbound data, positive lines 70, 73, 76, 79, 82, 90, 93, 96, 99, 102 ps [9:0] input primary southbound data, negative lines 71, 74, 77, 80, 83, 91, 94, 97, 100, 103 sn[13:0] output secondary northbound data, positive lines 142, 145, 148, 151, 154, 157, 160, 168, 171, 174, 177, 180, 183, 186 sn [13:0] output secondary northbound data, negative lines 143, 146, 149, 152, 155, 158, 161, 16, 172, 175, 178, 181, 184, 187 ss[9:0] input secondary southbound data, positive lines 190, 193, 196, 199, 202, 210, 213, 216, 219, 222 ss [9:0] input secondary southbound data, negative lines 191, 194, 197, 200, 203, 211, 214, 217, 220, 223 scl input serial presence detect (spd) clock input 120 sda input spd data input / output 119 sa[2:0] input spd address inputs, also used to slelect the dimm number in the amb 118, 239, 240 v id [1:0] nc voltage id : these pins must be unconnected for ddr2 - based fully buffered dimms v id [0] is v dd value : open = 1.8 v, gnd = 1.5 v ; v id [1] is v cc value : open = 1.5v, gnd = 1.2v 16, 136 reset input amb reset signal 17 rfu rfu reserved for future use 19, 20, 44, 45, 86, 87, 105, 106, 139, 140, 164, 165, 206, 207, 225, 226 v cc pwr amb core power and amb channel interface power (1.5 volt) 9, 10, 12, 13, 129, 130, 132, 133 v dd pwr dram power and amb dram i/o power (1.8volt) 1, 2, 3, 5, 6, 7, 108, 109, 111, 112, 113, 115, 116, 121, 122, 123, 125, 126, 127, 231, 232, 233, 235, 236 v tt pwr dram address/command/clcok termination power(v dd /2) 15, 117, 135, 237 v ddspd pwr spd power 238 v ss gnd ground 4, 8, 11, 14, 18, 21, 24, 27, 30, 33, 36, 39, 42, 43, 46, 47, 50, 53, 56, 59, 62, 65, 68, 69, 72, 75, 78, 81, 84, 85, 88, 89, 92, 95, 98, 101, 104, 107, 110, 114, 124, 128, 131, 134, 138, 141, 144, 147, 150, 153, 156, 159, 162, 163, 166, 167, 170, 173, 176, 179, 182, 185, 188, 189, 192, 195, 198, 201, 204, 205, 208, 209, 212, 215, 218, 221, 224, 227, 230, 234 dnu/m_test dnu the dnu/m_test pin provides an external connection r/cs a- d for testing the margin of vref which is produced by a voltage divider on the module. it is not intended to be used in normal system operation and must not be connected (dnu) in a sys- tem. this test pin may have other features on future card de- signs and if it does, will be included in this specification at that time. 137
rev. 1.51 january 2008 fbdimm ddr2 sdram 16 of 33 s 0 dqs0 dqs 0 dqs9 dm/ rdqs nu/ rdqs cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs4 dqs 4 dqs13 dm/ rdqs nu/ rdqs cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs1 dqs 1 dqs10 dm/ rdqs nu/ rdqs cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs5 dqs 5 dqs14 dm/ rdqs nu/ rdqs cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs2 dqs 2 dqs11 dm/ rdqs nu/ rdqs cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs6 dqs 6 dqs15 dm/ rdqs nu/ rdqs cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs3 dqs 3 dqs12 dm/ rdqs nu/ rdqs cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs7 dqs 7 dqs16 dm/ rdqs nu/ rdqs cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 dqs8 dqs 8 dqs17 dm/ rdqs nu/ rdqs cs dqs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 a m b pn0-pn13 pn 0-pn 13 ps0-ps9 ps 0-ps 9 dq0-dq63 cb0-cb7 dqs0-dqs17 dqs 0-dqs 8 scl sda sa1-sa2 reset sck/sck sn0-sn13 sn 0-sn 13 ss0-ss9 ss 0-ss 9 s0->cs (all sdrams) cke0->cke(all sdrams) odt->odt(all sdrams) ba0-ba2(all sdrams) a0-a15(all sdrams) ras (all sdrams) cas (all sdrams) we (all sdrams) ck/ck (all sdrams) v ss v cc v ref v tt v ddspd v dd d0-d8,spd,amb amb d0-d8 terminators spd, amb d0-d8, amb note : 1.dq-to i/o wiring may be changed within a byte. 2.there are two physical copies of each address/command/control/clock all address/command/control/clock v tt (populated as 1 rank of x8 ddr2 sdrams) a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp sa0 5.1 512mb, 64mx72 module - m395t6553ez4 5.0 fbdimm functional block diagram
rev. 1.51 january 2008 fbdimm ddr2 sdram 17 of 33 (populated as 2 rank of x8 ddr2 sdrams) s 1 dqs0 dqs 0 dqs9 dm/ rdqs nu/ rdqs cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs4 dqs 4 dqs13 dm/ rdqs nu/ rdqs cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs1 dqs 1 dqs10 dm/ rdqs nu/ rdqs cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs5 dqs 5 dqs14 dm/ rdqs nu/ rdqs cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs2 dqs 2 dqs11 dm/ rdqs nu/ rdqs cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs6 dqs 6 dqs15 dm/ rdqs nu/ rdqs cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs3 dqs 3 dqs12 dm/ rdqs nu/ rdqs cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs7 dqs 7 dqs16 dm/ rdqs nu/ rdqs cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 dqs8 dqs 8 dqs17 dm/ rdqs nu/ rdqs cs dqs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d9 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d10 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d11 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d12 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d13 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d14 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d15 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d16 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d17 s 0 a m b pn0-pn13 pn 0-pn 13 ps0-ps9 ps 0-ps 9 dq0-dq63 cb0-cb7 dqs0-dqs17 dqs 0-dqs 8 scl sda sa1-sa2 reset sck/sck sn0-sn13 sn 0-sn 13 ss0-ss9 ss 0-ss 9 s0->cs (d0-d8) cke0->cke(d0-d8) odt->odt(all sdrams) ba0-ba2(all sdrams) a0-a15(all sdrams) ras (all sdrams) cas (all sdrams) we (all sdrams) ck/ck (all sdrams) note : 1.dq-to i/o wiring may be changed within a byte. 2.there are two physical copies of each address/command/control/clock all address/command/control/clock v tt s1->cs (d9-d17) cke1->cke(d9-d17) v ss v cc v ref v tt v ddspd v dd d0-d17,spd,amb amb d0-d17 terminators spd, amb d0-d17, amb a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp sa0 5.2 1gb, 128mx72 module - m395t2953ez4
rev. 1.51 january 2008 fbdimm ddr2 sdram 18 of 33 a m b pn0-pn13 pn 0-pn 13 ps0-ps9 ps 0-ps 9 dq0-dq63 cb0-cb7 dqs0-dqs17 dqs 0-dqs 8 scl sda reset sck/sck sn0-sn13 sn 0-sn 13 ss0-ss9 ss 0-ss 9 s0->cs (d0-d17) cke0->cke(d0-d17) odt->odt(all sdrams) ba0-ba2(all sdrams) a0-a15(all sdrams) ras (all sdrams) cas (all sdrams) we (all sdrams) ck/ck (all sdrams) note : 1.dq-to i/o wiring may be changed within a byte. 2.there are two physical copies of each address/command/control/clock. 3. there are four physical copies of each clock. all address/command/control/clock v tt s1->cs (d18-d35) cke1->cke(d18-d35) v ss v cc v ref v tt v ddspd v dd d0-d35,spd,amb amb d0-d35 terminators spd, amb d0-d35, amb vss s 0 dqs0 dqs 0 dm cs dqs dqs dq0 dq1 dq2 dq3 i/o 0 i/o 1 i/o 2 i/o 3 d0 dqs9 dqs 9 dm cs dqs dqs dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 d9 dqs1 dqs 1 dm cs dqs dqs dq8 dq9 dq10 dq11 i/o 0 i/o 1 i/o 2 i/o 3 d1 dqs10 dqs 10 dm cs dqs dqs dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 d10 dqs2 dqs 2 dm cs dqs dqs dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 d2 dqs11 dqs 11 dm cs dqs dqs dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 d11 dqs3 dqs 3 dm cs dqs dqs dq24 dq25 dq26 dq27 i/o 0 i/o 1 i/o 2 i/o 3 d3 dqs12 dqs 12 dm cs dqs dqs dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 d12 dqs5 dqs 5 dm cs dqs dqs dq40 dq41 dq42 dq43 i/o 0 i/o 1 i/o 2 i/o 3 d5 dqs14 dqs 14 dm cs dqs dqs dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 d14 dqs4 dqs 4 dm cs dqs dqs dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d4 dqs13 dqs 13 dm cs dqs dqs dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 d13 dqs6 dqs 6 dm cs dqs dqs dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 d6 dqs15 dqs 15 dm cs dqs dqs dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 d15 dqs8 dqs 8 dm cs dqs dqs cb0 cb1 cb2 cb3 i/o 0 i/o 1 i/o 2 i/o 3 d8 dqs17 dqs 17 dm cs dqs dqs cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 d17 dqs7 dqs 7 dm cs dqs dqs dq56 dq57 dq58 dq59 i/o 0 i/o 1 i/o 2 i/o 3 d7 dqs16 dqs 16 dm cs dqs dqs dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 d16 s 1 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d18 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d19 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d20 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d21 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d23 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d22 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d24 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d26 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d25 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d27 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d28 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d29 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d30 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d32 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d31 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d33 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d35 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d34 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp sa1-sa2 sa0 (populated as 2 rank of x4 ddr2 sdrams) 5.3 2gb, 256mx72 module - m395t5750ez4
rev. 1.51 january 2008 fbdimm ddr2 sdram 19 of 33 table 6 : absoiute maximum ratings note : 1. stresses greater than those iisted may cause permanent damage to the device. this is a stress rating only, and functi onal operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. 2. ddr2 sdrams of fbdimm should require this specification. parameter symbol min max units note voltage on any pin relative to v ss v in , v out -0.3 1.75 v 1 voltage on v cc pin relative to v ss v cc -0.3 1.75 v 1 voltage v dd pin relative to v ss v dd -0.5 2.3 v 1 voltage on v tt pin relative to v ss v tt -0.5 2.3 v 1 storage temperature t stg -55 100 c1 ddr2 sdram device operating temperature(ambient) t case 085 c1,2 85 95 amb device operating temperature (ambient) t case 0110 c1,2 parameter symbol dram units average periodic refresh interval trefi 0 c t case 85 c 7.8 s 85 c < t case 95 c 3.9 s table 8 : timing parameters note : 1. defined in fb-dimm architecture and protocol spec 2. clocks defined as core clocks = 2x sck input 3. @ ddr2-667 - measured from beginning of frame at southbound input to ddr clock output that latches the first command of a fr ame to the drams 4. @ ddr2-667 - measured from latest dqs input amb to start of matching data frame at northbound fb-dimm outputs. parameter symbol min typ. max. units notes ei assertion pass-thru timing tei propagatet 4 clks - ei deassertion pass-thr u timing teid bitlock clks 2 ei assertion duration tei 100 clks 1,2 fbd cmd to ddr clk out that latches cmd 8.1 ns 3 fbd cmd to ddr write tbd ns ddr read to fbd (last dimm) 5.0 ns 4 resample pass-thru time 1.075 ns resynchpass-thru time 2.075 ns bit lock interval tbitlock 119 frames 1 frame lock interval tframelock 154 frames 1 table 7 : input dc operating conditions note : 1. applies for smb and spd bus signals. 2. applies for amb cmos signal reset . 3. for all other amb related dc parameters, please refer to the high-speed differential link interface specification. parameter symbol min nom max units notes amb supply voltage v cc 1.4551.501.575v ddr2 sdram supply voltage v dd 1.7 1.8 1.9 v termination voltage v tt 0.48 x v dd 0.50 x v dd 0.52 x v dd v eeprom supply voltage v ddspd 3.0 3.3 3.6 v spd input high (iogic 1) voltage v ih (dc) 2.1 v ddspd v1 spd input low (logic 0) voltage v il (dc) 0.8 v 1 reset input high (logic 1) voltage v ih (dc) v 2 reset input low (logic 0) voltage v il (dc) 0.5 v 1 leakage current (reset) i l -90 90 ua 2 leakage current (link) i l -5 5 ua 3 6.0 electrical characteristics
rev. 1.51 january 2008 fbdimm ddr2 sdram 20 of 33 table 9 : power specification parameter and test condition symbol conditions power supply units icc_idle_0 idle current, single or last dimm l0 state, idle (0 bw) primary channel enabled, secondary channel disabled cke high. command and address lines stable. dram clock active. @1.5v ma idd_idle_0 @1.8v ma idd_idle_0 total power w icc_idle_1 idle current, first dimm l0 state, idle (0 bw) primary and secondary channels enabled cke high. command and address lines stable. dram clock active. @1.5v ma idd_idle_1 @1.8v ma idd_idle_1 total power w icc_active_1 active power l0 state. 50% dram bw, 67% read, 33% write. primary and secondary channels enabled. dram clock active, cke high. @1.5v ma idd_active_1 @1.8v ma idd_active_1 total power w icc_active_2 active power, data pass through l0 state. 50% dram bw to downstream dimm, 67% read, 33% write. primary and secondary channels enabled cke high. command and address lines stable. dram clock active. @1.5v ma idd_active_2 @1.8v ma idd_active_2 total power w idd_training (for amb spec, not in spd) training primary and secondary channels enabled. 100% toggle on all channel lanes drams idle. 0 bw. cke high, command and address lines stable. dram clock active. @1.5v ma idd_training (for amb spec, not in spd) @1.8v ma idd_training total power w
rev. 1.51 january 2008 fbdimm ddr2 sdram 21 of 33 table 10-1 : power specification (vdd max = 1.900v, vcc max = 1.575v) table 10-2 : power specification (vdd max = 1.900v, vcc max = 1.575v) note : 1. fbdimm power was calculated on the basis of dram and amb values in datasheet. symbol 512mb (m395t6553ez4) notes unit d55 d56/d51 d57 e65 e66/e61 e67 f76/e76 (pc2-4200) (pc2-5300) (pc2-6400) icc_idle_0 2200 2200 2090 2600 2600 2350 tbd @1.5v ma idd_idle_0 970 970 396 1015 1015 451 @1.8v ma p_idle_0 5.308 5.308 4.044 6.024 6.024 4.558 w icc_idle_1 3000 3000 2930 3400 3400 3220 @1.5v ma idd_idle_1 970 970 396 1015 1015 451 @1.8v ma p_idle_1 6.568 6.568 5.367 7.284 7.284 5.928 w icc_active_1 3400 3400 2930 3900 3900 3220 @1.5v ma idd_active_1 2230.6 2230.6 1809.6 2425.9 2425.9 2031.9 @1.8v ma p_active_1 9.593 9.593 8.053 10.752 10.752 8.932 w icc_active_2 3200 3200 2930 3700 3700 3220 @1.5v ma idd_active_2 970 970 396 1015 1015 451 @1.8v ma p_active_2 6.883 6.883 5.367 7.756 7.756 5.928 w icc_training 3500 3500 3050 4000 4000 3380 @1.5v ma idd_training 970 970 1149 1015 1015 1221 @1.8v ma p_training 7.356 7.356 6.987 8.229 8.229 7.643 w symbol 1gb (m395t2953ez4) notes unit d55 d56/d51 d57 e65 e66/e61 e67 f76/e76 (pc2-4200) (pc2-5300) (pc2-6400) icc_idle_0 2200 2200 2090 2600 2600 2350 tbd @1.5v ma idd_idle_0 1240 1240 666 1330 1330 766 @1.8v ma p_idle_0 5.821 5.821 4.557 6.622 6.622 5.157 w icc_idle_1 3000 3000 2930 3400 3400 3220 @1.5v ma idd_idle_1 1240 1240 666 1330 1330 766 @1.8v ma p_idle_1 7.081 7.081 5.880 7.882 7.882 6.527 w icc_active_1 3400 3400 2930 3900 3900 3220 @1.5v ma idd_active_1 2500.6 2500.6 2079.6 2740.9 2740.9 2346.9 @1.8v ma p_active_1 10.106 10.106 8.566 11.350 11.350 9.531 w icc_active_2 3200 3200 2930 3700 3700 3220 @1.5v ma idd_active_2 1240 1240 666 1330 1330 766 @1.8v ma p_active_2 7.396 7.396 5.880 8.355 8.355 6.527 w icc_training 3500 3500 3050 4000 4000 3380 @1.5v ma idd_training 1240 1240 1419 1330 1330 1536 @1.8v ma p_training 7.869 7.869 7.500 8.827 8.827 8.242 w
rev. 1.51 january 2008 fbdimm ddr2 sdram 22 of 33 table 10-3 : power specification (vdd max = 1.900v, vcc max = 1.575v) note : 1. fbdimm power was calculated on the basis of dram and amb values in datasheet. symbol 2gb (m395t5750ez4) notes unit d55 d56/d51 d57 e65 e66/e61 e67 f76/e76 (pc2-4200) (pc2-5300) (pc2-6400) icc_idle_0 2200 2200 2090 2600 2600 2350 tbd @1.5v ma idd_idle_0 1980 1980 1206 2160 2160 1396 @1.8v ma p_idle_0 7.227 7.227 5.583 8.199 8.199 6.354 w icc_idle_1 3000 3000 2930 3400 3400 3220 @1.5v ma idd_idle_1 1980 1980 1206 2160 2160 1396 @1.8v ma p_idle_1 8.487 8.487 6.906 9.459 9.459 7.724 w icc_active_1 3400 3400 2930 3900 3900 3220 @1.5v ma idd_active_1 3980.6 3980.6 3159.6 4340.6 4340.6 3546.6 @1.8v ma p_active_1 12.918 12.918 10.618 14.390 14.390 11.810 w icc_active_2 3200 3200 2930 3700 3700 3220 @1.5v ma idd_active_2 1980 1980 1206 2160 2160 1396 @1.8v ma p_active_2 8.802 8.802 6.906 9.932 9.932 7.724 w icc_training 3500 3500 3050 4000 4000 3380 @1.5v ma idd_training 1980 1980 1959 2160 2160 2166 @1.8v ma p_training 9.275 9.275 8.526 10.404 10.404 9.439 w
rev. 1.51 january 2008 fbdimm ddr2 sdram 23 of 33 table 11 : v tt currents description symbol typ max units idle current, ddr2 sdram device power down itt1 500 700 ma active power, 50% ddr2 sdram bw itt2 500 700 ma table 12 : reference cl ock input specifications note : 1.133mhz for pc2-4200, 166mhz for pc2-5300 and 200mhz for pc2-6400. 2. measured with ssc disabled. 3. measured differentially through the range of 0.175v to 0.525v. 4. the crossing point must meet the absolute and re lative crossing point spec ification simultaneously. 5. v cross_rel_(min) and v cross_rel(max) are derived using the following calculation : min = 0.5(v havg -0.710)+0.250;and max=0.5(v havg -0.710)+0.550, where vhavg is the average of v sck-highm. 6. measured with a single-ended input voltage of 1v. 7. applies to reference clocks sck and sck . 8. difference between sck and sck input. 9. t1 = [tdatapath-tclockpath](excluding pll loop delays). this parameter is not a dire ct clock output parameter but in indirec tly determines the clock output parameter t ref-jitter. 10. the net transport delay is the difference in time of fli ght between associated data and clock paths. the data path is defin ed from the reference clock source, through the tx, to data arrival at the data dampling point in the rx. the clock path is defined from the reference cloc k source to clock arrival at the same sampling point. the path delays are caused by copper trace routes. on-chip routing, on-chip buffering, etc. they in clude the time-of flight of interpolators or other clock adjustment mechanisms. they do not include the phas e delays caused by finite pll loop bandwidth because these de- lays are modeled by the pll transfer functions. 11. direct measurement of phase jitter records over 1016 periods is impractical. it is expected that the jitter will be measure d over a smaller, yet statistically significant, sample size and the total jitter at 10 16 samples extrapolated from an estimate of the sigma of the random jitter components. 12. measured with ssc enabled on reference clock generator. 13. as measured after the phase jitter filter. this number is se parate from the receiver jitter budget that is defined by the t rxtotal - min parameters. parameter symbol values units note min max reference clock frequency @3.2 gb/s (nominal 133.33 mhz) frefclk-3.2 126.67 133.40 mhz 1.2 reference clock frequency @4.0 gb/s (nominal 166.67 mhz) frefclk-4.0 158.33 166.75 mhz 1.2 reference clock frequency @4.8 gb/s (nominal 200 mhz) frefclk-4.8 190.00 200.10 mhz 1.2 rise time, fall time t sck-rise , t sck-fall 175 700 ps 3 voltage high v sck-high 660 850 mv voltage low v sck-low -150 mv absolute crossing point v cross-abs 250 550 mv 4 relative crossing v cross-rel calculated calculated 4,5 percent mismatch between rise and fall times t sck-rise-fall-match -10% duty cycle of reference clock t sck-dutycycle 40 60 % clock leakage current i i-ck -10 10 ua 6,7 clock input capacitance c i-ck 0.5 2 pf 7 clock input capacitance delta c i_ck(d) -0.25 0.25 pf 8 transport delay t1 5 ns 9, 10 phase jitter sample size nsample 10 16 periods 11 reference clock jitter, filtered t ref-jitter 40 ps 12,13
rev. 1.51 january 2008 fbdimm ddr2 sdram 24 of 33 table 13 : differential transmitter output specifications parameter symbol values units comments min max differential peak-to-peak output voltage for large voltage swing v tx-diffp-p_l 900 1,300 mv eq1, note1 differential peak-to -peak output voltage for requ- lar voltage swing v tx-diffpp-p_r 800 mv eq1, note1 differential peak-to-peak output voltage for small votage swing v tx-diffp-p_s 520 mv eq1, note1 dc common code output voltage for large voltage swing v tx-cm_l 375 mv eq2, note1 dc common code output voltage for small volt- age swing v tx-cm_s 135 280 mv eq2, note1,2 de-emphasized differential output voltage ratio for -3.5 db de-emphasis v tx-de-3.5-ratio -3.0 -4.0 db 1,3,4 de-emphasized differential output voltage ratio for -6.0 db de-emphasis v tx-de-6.0-ratio -5.0 -7.0 db 1,2,3 ac peak-to-peak common mode output voltage for large swing v tx-cm-acp-p-l 90 mv eq7, note1,5 ac peak-to-peak common mode output voltage for regular swing v tx-cm-acp-p-r 80 mv eq7, note1,5 ac peak-to-peak common mode output voltage for small swing v tx-cm-acp-p-s 70 mv eq7, note1,5 maximum single-ended voltage in ei condition dc+ac v tx-idle-se 50 mv 6 maximum single-ended voltage in ei condition dc+ac v tx-idle-se-dc 20 mv 6 maximum peak-to-peak differential voltage in ei condition v tx-idle-diffp-p 40 mv single-ended voltage (w.r.t. vss) on d+/d- v tx-se -75 750 mv 1,7 mimimum tx eye width, 3.2 and 4.0 gb/s t tx-eye-min ui 1,8 mimimum tx eye width 4.8 gb/s t tx-eye-min4.8 ui 1,8 maximum tx deterministic jitter, 3.2 and 4.8gb/s t tx-dj-dd 02 ui 1,8,9 insantaneous pulse width t tx-pulse 0.85 ui 10 differential tx output rise/fall time t tx-rise t tx-fall 30 90 ps 20-80% voltage, note1 mismatch between rise and fall times t tx-rf-mismatch 20 ps differential return loss rl ttx-diff 8 db 1 ghz-2.4 ghz, note 11 common mode return loss rl tx-cm 6 db 1 ghz-2.4 ghz, note 11 transmitter termination impender r tx 41 55 12 d+/d-tx impedance difference r tx-match-dc 4% eq 4, boundaries are applied sepa- rately to high and low output voltage states lane-to lane skew at tx l tx-skew1 100+3ui ps 13, 15 lane-to lane skew at tx l tx-skew2 100=2ui ps 14, 15
rev. 1.51 january 2008 fbdimm ddr2 sdram 25 of 33 table 14 : differential re ceiver input specifications note : 1. specified at the package pins into a ti ming and voltage compliant test setup. note that signal levels at the pad will be low er than at the pin. 2. single-ended voltages below that value that are simultaneously detected on d+ and d-are interpreted as the electrical idle c ondition. worst-case mar- gins are determined for the case with transmitter using small voltage swing. 3. multiple lanes need to detect the el conditi on before the device can act upon the el detection. 4. specified at the package pins into a timing and voltage compliance test setup. 5. the single-pulse mask provides suffcient symbol energy for reliable rx reception. each symbol must comply with both the sing le-pulse mask and the cumulative eyemask. 6. the relative amplitude ratio limit between adjacent symbols prev ents excessive intersymbol interference in the rx. each symb ol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols. 7. this number does not include the effe cts of ssc or reference clock jitter. 8. this number includes setup and hold of the rx sampling flop. 9. defined as the dual-dirac deterministic timing error. 10. allows for 15 mv dc offset between transmit and receive devices. parameter symbol values units comments min max differential peak-to-peak input voltage for large volt- age swing v rx-diffp-p 170 1300 mv eq 5, note1 maximum single-ended voltage in el condition v rx-idle-se 65 mv 2,3 maximum single-ended voltage in ei condition (dc only) v rx-idle-se-dc 35 mv 2,3 maximum peak-to-peak differential voltage in el condition v rx-idle-diffp-p 65 mv 3 single-ended voltage (w.r.t. v ss ) on d+/d- v rx-se -300 900 mv 4 single-pulse peak differential input voltage v rx-diff-pulse 85 mv 4,5 amplitude ratio between adjacent symbols v rx-diff-adj-ratio 4.0 4,6 maximum rx inherent timing error t rx-tj-max 0.4 ui 4,7,8 maximum rx inherent deter ministic timing error t rx-dj-dd 0.3 ui 4,7,8,9 differential rx input rise/fall time t rx-pw-zc 0.55 ui 4,5 common mode fo the input voltage t rx-pw-ml 0.2 ui 4.5 differential rx output rise/fall time t rx-rise t rx-fall 50 ps 20~80% voltage common mode of input voltage v rx-cm 120 400 mv eq 6, note1, 10 ac peak-to-peak common mode of input voltage v rx-cm-acp-p 270 mv eq 7, note 1 ratio of v rx-cm-acp-p to minimum v rx-diffp-p v rx-cm-eh-ratop 45 % 11 differential return loss rl rx-diff 9 db 1ghz-2.4 ghz, note 12 common mode return loss rl rx-cm 6 db 1ghz-2.4 ghz, note 12 rx termination impedance r rx 41 55 ? 13 d+/d- rx impedance difference r rx-match-dc 4% eq 8 lane-to lane pcb skew at rx l rx-pcb-skew 6ui lane-to-lane skew at the receiver that must be tolerated. note 14 minimum rx drift tolerance t rx-drift 400 ps 15 minim data tracking 3db bandwidth f trk 0.2 mhz 16 electrical idle entry detect time t ei-entry-detect 60 ns 17 electrical idle exit detect time t ei-exit-detect 30 ns bit error ratio ber 10 -12 18
rev. 1.51 january 2008 fbdimm ddr2 sdram 26 of 33 11. the received differential signal must sa tisfy both this ratio as well as the absolute maximum ac peaktopeak common mode spe cification. for example, if vrx-diffp-p is 200 mv, the maximum ac peak-to peak common mode is the lesser of (200 mv*0.45=90 mv)and vrx-cm-ac-p-p. 12. one of the components that contribute to the deterioration of the return loss is the esd structure which needs to be carefu lly designed. 13. the termination small signal resistance; tolerance across voltage from 100 mv to 400 mv shall not exceed +/-5 w with regard to the average of the values measured at 100 mv and at 400 mv for that pin. 14. this number represents the lane-to-lane skew between tx and rx pins and does not include the tr ansmitter output skew from t he component of the end-to-end channel skew in the amb specification. 15. measured from the reference clock edge to the center of the i nput eye. this specification mu st be met across specified volt age and temperature ranges for a single component. drift rate of change is signific antly below the tracking capability of the receiver. 16. this bandwidth number assume the specified minimum data transition density. maximum jitter at 0.2 mhz is 0.05 ui, 17. the specified time includes the time re quired to forward the el entry condition. 18. ber per differential lane. v rx-diffp-p = 2x[v rx-d +-v rx-d- ] (eq5) (v rx-cm = dc(avg) of [v rx-d+ + v rx-d- ] /2) (eq 6) v rx-cm-ac =((max[v rx-d+ + v rx-d )/2)((min [v rx-d+ + v rx-d- )/2) (eq 7) r rx-match-dc = 2x((r rx-d+ -r rx-d- )/(r rx-d+ + r rx-d- ) (eq 8)
rev. 1.51 january 2008 fbdimm ddr2 sdram 27 of 33 figure16 : amb initialization flow diagram tranining (ts0) disable (ei) calibrate (1?s) recalibrate (nop2) testing (ts1) polling (ts2) config (ts3) l0 (ei) l0s (ei) power-up the states in the amb initia lization flow diagram are : disable - the channel is inactive and the interface signals are in a low power electrical idle condition. training - the initial bit alignment and frame alignment training is done in this state. testing - each bit lane is individually tested in this state. polling - the channel capabilities of the individual amb devices are communicated in this state. config - the channel width configuration is comm unicated to the amb devices in this state. l0 - the channel is active and frames of information are flowing between the host and the amb devices . recalibrate - the channel is momentarily idled to allow tx and rx circuits to be recalibrated. l0s - the channel is in a low-laten cy power saving condition. (optional) each bit lane is initialized (mosly) independently to support fa ult tolerance. the transitions in the figure represent the tran sitions of the amb core logic state machine and are taken when the transition event is detected on the minimum required number of southound bi t lanes. the chain of fbd links connecting the host the ambs must each be initialized to esabish the timing for broadcasting data frames in the southbound direction and for merging data frame in the nort hbound direction. the ambs on the channel are generally initi alized as a group but because each amb is individ ually addressable many altemate may altemate initialization sequences may be employed . 7.0 channel initialization this chapter defines the proces s of initializing the fbd channel. the fbd initia lzation process generally follows the top to bo ttom se- quence of state transitions shown in the high level amb initialization flow diagram in figure the host must sequence the amb de vices through the disable, (back to disable), training, testing, and po lling states in order to transiti on the ambs into the active c hannel l0 state. the value in parenthesis in each state bubble indicate s the condition/activity of the links during these states.
rev. 1.51 january 2008 fbdimm ddr2 sdram 28 of 33 133.35 126.85 d 18.80 2.0 5.175 67 51 c 9.50 b 123 a e 30.35+/-0.15 2x dia. 2.0 +0.1/-0 2x 3.25 2x 2.50 min 4x 3.00+/-0.1 figure 17 : fbdimm physical dimension -1 (for pcb) : 64mbx8 based 64mx72 module (1rank) amb 3.80 2.50 5.0 1.50 detail a 2.50+/-0.20 max 0.178 detail b 120 3.9 detail c 1.25 2.6 1.19 detail d 1.19 2.25 6.0 0.8 +/- 0.05 0.20+/-0.15 1.00 r0.75 2.50 detail e 1.19 2.25 r0.595 r0.595 m395t6553ez4
rev. 1.51 january 2008 fbdimm ddr2 sdram 29 of 33 units : millimeters 8.2 max 1.27 0.10 back 3.0 max figure 18 : fbdimm physical dimension -2 (for heat spreader): 64mbx8 based 64mx72 module (1rank) m395t6553ez4 133.35 30.35 0.15 67 123 51
rev. 1.51 january 2008 fbdimm ddr2 sdram 30 of 33 133.35 126.85 d 18.80 2.0 5.175 67 51 c 9.50 b 123 a e 30.35+/-0.15 2x dia. 2.0 +0.1/-0 2x 3.25 2x 2.50 min 4x 3.00+/-0.1 amb 3.80 2.50 5.0 1.50 detail a 2.50+/-0.20 max 0.178 detail b 120 3.9 detail c 1.25 2.6 1.19 detail d 1.19 2.25 6.0 0.8 +/- 0.05 0.20+/-0.15 1.00 r0.75 2.50 detail e 1.19 2.25 r0.595 r0.595 figure 19 : fbdimm physical dimension -1 (for pc b) : 64mbx8 based 128mx72 module (2rank) m395t2953ez4
rev. 1.51 january 2008 fbdimm ddr2 sdram 31 of 33 figure 20 : fbdimm physical dimension -2 (for he at spreader) : 64mbx8 based 128mx72 module (2rank) m395t2953ez4 units : millimeters 8.2 max 1.27 0.10 back 3.0 max 133.35 30.35 0.15 67 123 51
rev. 1.51 january 2008 fbdimm ddr2 sdram 32 of 33 133.35 126.85 d 18.80 2.0 5.175 67 51 c 9.50 b amb 123 a e 30.35+/-0.15 2x dia. 2.0 +0.1/-0 2x 3.25 2x 2.50 min 4x 3.00+/-0.1 3.80 2.50 5.0 1.50 detail a 2.50+/-0.20 max 0.178 detail b 120 3.9 detail c 1.25 2.6 1.19 detail d 1.19 2.25 6.0 0.8 +/- 0.05 0.20+/-0.15 1.00 r0.75 2.50 detail e 1.19 2.25 r0.595 r0.595 figure 21 : fbdimm physical dimension -1 (for pcb) : 128mbx4 based 256mx72 module (2rank) m395t5750ez4
rev. 1.51 january 2008 fbdimm ddr2 sdram 33 of 33 figure 22 : fbdimm physical dimension -2 (for heat spreader) : 128mbx4 based 256mx72 module (2rank) m395t5750ez4 units : millimeters 8.2 max 1.27 0.10 back 3.0 max 133.35 30.35 0.15 67 123 51

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